RISC-V Processor

Overview

Implemented a Verilog RISC-V processor with ISA support, core control logic, and staged execution flow.

Challenge

Translate architecture fundamentals into a correct and testable processor implementation under tight correctness constraints.

System Design

• Modular datapath and control design aligned with core RISC-V instruction behavior.
• Pipeline-oriented stage boundaries for instruction flow and state updates.
• Instruction decode and execution units built for traceable debugging.

Build Details

• Implemented control sequencing for arithmetic, memory, and branch-style operations.
• Validated execution outcomes with waveform inspection and directed tests.
• Refined module interfaces to simplify iterative verification.

Outcomes

• Delivered a working processor core with documented design assumptions and reproducible simulation behavior.

Tech Stack