32kBit SRAM Design

Overview

Designed a 6T SRAM cell array in Cadence and integrated word-wise sleep functionality for power-aware behavior.

Challenge

Balance stability, performance, and low-power behavior in a compact SRAM implementation.

System Design

• 6T cell baseline with array-level organization for 32kBit storage.
• Word-wise sleep integration for dynamic power reduction.
• Simulation flow covering read/write and retention behavior.

Build Details

• Built and tuned lumped circuit models for key operation modes.
• Verified behavior through Cadence simulation under representative conditions.
• Documented design tradeoffs around speed, robustness, and power.

Outcomes

• Produced a simulation-backed SRAM design with explicit low-power strategy.

Tech Stack